1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a memory cell array structure in which nonvolatile memory cells having a lamination gate structure are arrayed in a matrix manner and more particularly to a nonvolatile semiconductor memory device in which a data hold characteristic of the memory cell is improved and a reading error of data is removed.
2. Description of the Related Art
Generally, in an EEPROM (Electrically Erasable Programmable ROM), a MOS transistor having a lamination gate structure is used as a memory cell. There is known an EPROM with tunnel oxide cell, which is called as an ETOX (registered trademark of U.S. Intel) type cell.
Other than the above cell, there are used an FLOTOX (Floating Gate Tunnel Oxide) cell comprising two transistors, that is, a memory cell transistor and a selective transistor, an ACEE (Advanced Contactless EEPROM) cell in which the selective transistor constituting the FLOTOX is omitted and a drain contact is used in common, or an SISOS (Sidewall Select-gate On Source Side) cell having a side wall selective transistor in a source side.
The following will explain the tunnel oxide type cell among the above conventional cells.
More specifically, in the tunnel oxide type cell, there are formed a source region in which a source voltage is applied to a surface of a semiconductor substrate, a drain region to which a drain voltage is applied, and a channel region between both regions. On the channel region, a floating gate is formed through a gate insulating film. A control gate is laminated on the floating gate through an interlayer insulating film. In the above-structured EPROM with a tunnel oxide cell, data writing is performed by a bit unit, and data erasing is performed by an all bit batch erasing or a selected block unit.
On the other hand, in cell data reading, a low source voltage VD, for example, 0V is applied to the source, and an intermediate drain voltage VD, for example, 1V is applied to the drain. In this case, if a reading voltage Vcc to be applied to the control gate is higher than a reverse voltage of a cell channel, which is a cell threshold voltage, in other words, there is used a cell in which no electron is implanted into the floating gate, current can flow into the channel region and cell data is discriminated as "1." If the electron is implanted into the floating gate, the threshold voltage is higher than the read voltage, no current flows into the channel region, and cell data is discriminated as "0." A data reading control is performed as mentioned manner.
In the above conventional tunnel oxide type memory cell transistor, the threshold value in which the floating gate is not charged either positively or negatively, that is, the floating gate is in an electrically neutral state, was set to an applied voltage to be applied to the control gate at the time of data reading, that is, the applied voltage was set to be lower than 5V. This can be understood from, for example, FIG. 9 of "1991 International Electron Device Meeting Technical Digest." Due to this, if the positive ion comes into the floating gate when the electron is implanted into the floating gate, the threshold value is gradually decreased even if the threshold value is set to be higher than the reading voltage of 5V. Finally, the threshold voltage becomes lower than the reading voltage of 5V. This means that data hold, which is in the state that the electron is implanted in the floating gate, is not in an unfavorable state.
In the above conventional EEPROM, there was an disadvantage in which even if either the floating gate is in the neutral state or the electron is implanted into the floating gate, erroneous data reading will occur since the positive ion comes into the floating gate, which is in the neutral state, from the external portion.
Moreover, in the conventional memory cell array, there was an advantage in which the drain of the memory cell transistor is connected to the bit line through the select gate and degree of freedom in reading data is expanded. However, there was an disadvantage in which a space for arranging the select gate is required.